1. Field of the Invention
The present invention generally relates to programmable logic devices, and more particularly, to the efficient distribution of signals which span across Logic Array Block (LABs) in programmable logic devices to improve the efficiency of distributing logic within the device.
2. Description of Related Art
A Programmable Logic Device (PLD) is a semiconductor integrated circuit that contains fixed logic circuitry that can be programmed to perform a host of logic functions. In the semiconductor industry, PLDs are becoming increasingly popular for a number of reasons. Due to the advances of chip manufacturing technology, application specific integrated circuits (ASICs) designs have become incredibly complex. This complexity not only adds to design costs, but also the duration of time needed to develop an application specific design. To compound this problem, product life cycles are shrinking rapidly. As a result, it is often not feasible for original equipment manufacturers (OEMs) to design and use ASICs. OEMs are therefore relying more and more on PLDs. The same advances in fabrication technology have also resulted in PLDs with improved density and speed performance. Sophisticated programming software enables complex logic functions to be rapidly developed for PLDs. Furthermore, logic designs generally can also be easily migrated from one generation of PLDs to the next, further reducing product development times. The closing of the price-performance gap with ASICs and reduced product development times makes the use of PLDs compelling for many OEMs.
Most PLDs contain a two-dimensional row and column based architecture to implement custom logic. A series of row and column interconnects, typically of varying length and speed, provide signal and clock interconnects between blocks of logic on the PLD. The blocks of logic, often referred to as Logic Array Blocks or LABs, contain one or more basic logic elements used to implement logic functions on the device. The basic logic elements are referred to by a variety of names such names as Logic Elements (LEs), Adaptive Logic Modules (ALMs), or Complex or Configurable Logic Blocks (CLBs). Hereafter, for the sake of simplicity the basic logic elements will be referred to as “Logic Elements” or LEs. Regardless of the variety, the logic elements usually include one or more look up table (LUTs), registers for generating registered logic outputs, adders and other circuitry to implement various logic and arithmetic functions.
The Stratix® device is one type of commercially available PLD, offered by Altera Corporation, assignee of the present application. The Stratix® PLD includes an array of LABs arranged in rows and columns and interconnected by horizontal and vertical lines of various lengths. Most relevant to the present invention, each LAB includes, among other elements, 10 logic elements or LEs, a local interconnect, and LAB wide control signals. The local interconnect transfers signals between LEs in the same LAB. The LAB wide control signals include two clocks, two clock enables, two asynchronous clears (ACLR), synchronous clear (SCLR), asynchronous preset/load, synchronous load (SLOAD) and add/subtract load signals. Some of the aforementioned signals are considered to be “LAB-wide” because they are globally applied to each Logic Element in the LAB. With the current Stratix architecture, there is no way to individually apply one of these control signals to one logic element but not the other logic elements in the LAB.
The SCLR signal controls the output of the register in each Logic Element in the LAB. If the SCLR signal is asserted, the output of every register in each Logic Element is force to a logic zero. If the SCLR signal is not asserted, then register output equals the output of the associated Look Up Table (LUT) in each Logic Element respectively. If the SLOAD control signal is asserted, then the output of each register is equal to SDATA respectively. SDATA is either a pre-designated value or it is a data value derived from some other function or location on the device. When the SLOAD signal is not asserted, then again the output of the registers of each Logic Element is the output of the associated Look Up Table respectively.
The SCLR and SLOAD signals are typically used when the Logic Elements of a LAB are configured to operate as counters. For example, when the SCLR signal in the LAB is asserted, the registered output of each Logic Element is forced to zero, effectively resetting the counter. The SLOAD and SDATA signals are used when counter is to be reset to some non-zero value. For example, if the counter is to be reset to the value (1, 0, 1, 0, 1 . . . 0), then the SDATA signals are set to (1, 0, 1, 0, 1 . . . 0) and the SLOAD signal is asserted. When this occurs, the output of the registers of each Logic Element in the LAB will be set to (1, 0, 1, 0, 1 . . . 0) respectively.
The problem with the aforementioned arrangement is that the LAB wide control signals are commonly shared among all of the Logic Elements in the LAB. There is currently no way to individually apply the control signals to one or more select Logic Elements in a LAB. This is particularly troublesome with regard to the efficient use of the hardware resources on the PLD in implementing logic. For example, consider a LAB with ten (10) Logic Elements that is configured to implement a six (6) bit wide counter. In this situation, the registers of six of the Logic Elements are used for the counter. The remaining four Logic Elements, however, can only be used for implementing combinational logic since their registers are controlled by the LAB wide control signals SCLR and/or SLOAD. It is therefore difficult to use the remaining registers for implementing logic. The ability or efficiency to “pack” the LAB with logic is therefore significantly reduced.
One known remedy for the above-mentioned packing problem is to apply the LAB wide control signals such as SCLR, SLOAD, ACLR, etc. individually to each Logic Element in the LAB. As a practical matter, however, to do so is very expensive in terms of an actual silicon implementation. The LAB would require significantly more resources such as interconnect, input muxes, configuration bits, etc. to provide a full set of the LAB wide control signals individually to each Logic Element in the LAB. While applying the control signals to each Logic Element in the LAB would substantially eliminate the logic packing issue, it would create a host of other problems. Additional interconnect, muxing, and configuration bits would be needed within the LAB to individually apply the LAB wide control signals to each Logic Element in the LAB. While the LAB wide control signals could be individually applied to each Logic Element, PLD designers have chosen not to because the overhead in terms of the use of space and resources within the LAB are too significant.
A PLD architecture with improved distribution of control signals within a region including one or more logic elements to increase the packing of logic among the logic elements in the region is therefore needed.